A flash or block erase memory (flash memory), such as Flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide Semiconductor (MOS) memory cells that are field effect transistors (FETs). Each FET, or flash, memory cell includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. The flash memory cell provides for nonvolatile data storage.
Prior Art FIG. 1 illustrates a typical configuration of a flash memory cell 100. The transistor typically consists of a thin, high-quality tunnel oxide layer 140 sandwiched between a conducting polysilicon floating gate 130 and a crystalline silicon semiconductor substrate 170. The tunnel oxide layer is typically composed of silicon oxide (SixOy). The substrate 170 includes a source region 150 and a drain region 160 that can be separated by an underlying channel region. A control gate 110 is provided adjacent to the floating gate 130, and is separated by an interpoly dielectric 120. Typically, the interpoly dielectric 120 can be composed of an oxide-nitride-oxide (ONO) structure.
The flash memory cell 100 stores data by holding charge within the floating gate 130. In a write operation, charge can be placed on the floating gate 130 through hot electron injection, or Fowler-Nordheim (F-N) tunneling. In addition, F-N tunneling can be typically used for erasing the flash memory cell 100 through the removal of charge on the floating gate 130.
As flash memory technology progresses, the density of the memory cells, as well as, the speed of the flash memory increases. However, the continued reduction in size of the conventional floating gate flash memory cell 100 has been essentially limited by two primary effects: first, a minimum thickness of the tunnel oxide dielectric 140 that limits capacitance of the flash memory cell 100; and second, the inability to reduce the higher operating voltages affecting the flash memory cell 100.
First, in order to improve short channel effects and to increase core gain (Id/W), the unit area capacitance of the tunnel oxide dielectric 140 could be increased. Correspondingly, a higher unit area capacitance also leads to better retention of charge within the floating gate 130.
In the prior art, the thickness of the tunnel oxide dielectric 140 between the floating gate 130 and the substrate 170 can be reduced to obtain higher unit area capacitance. Unit area capacitance is inversely related to the thickness of the tunnel oxide dielectric 140. However, a thinner tunnel oxide dielectric 140 also leads to an increase in tunneling probability. This eventually leads to increased charge loss in the floating gate 130 over the lifetime of the flash memory device 100. As a result, a minimum thickness of approximately 10 nanometers (nm) is necessary to negate long term reliability degradation due to increased probability of charge loss due to thinner and thinner tunnel oxide layers 140 composed of silicon oxide. Thus, unit area capacitance of the tunnel oxide dielectric 140 is limited by the minimum thickness of the tunnel oxide dielectric 140.
Second, as the flash memory cell 100 becomes smaller and smaller, a corresponding reduction in operating voltage over the flash memory cell 100 must occur in order to maintain long-term longevity of the flash memory cell 100. A reduction in physical size of the flash memory cell 100 must be accompanied by a reduction in operating voltages to maintain relatively proportional electrical fields within the flash memory cell 100. For example, subjecting the smaller flash memory device to the same operating voltages as the previously larger device would result in quicker breakdown of the device in the channel region across the source region 150 and the drain region 160.
For example, programming and erasing of the flash memory device can involve electron injection by either F-N tunneling or channel hot electron (CHE) injection. Both F-N tunneling and CHE injection are controlled by the barrier height of the tunnel oxide dielectric 140. As such, in order to reduce operating voltages, a barrier energy of the tunnel oxide dielectric 140 must be reduced.
Conventionally, the tunnel oxide dielectric 140 that is composed of silicon oxide gives a very high barrier energy. Prior Art FIG. 2 is a diagram illustrating the electron and hole barrier energies for silicon oxide tunnel oxide dielectric 140 having a dielectric constant ξoxide of 3.9. As illustrated, the barrier height for electron movement is approximately 3.15 electron volts (eV). The high operating voltages required for electrons to overcome the barrier height of 3.15 eV precludes continued reduction in the size of the flash memory cell 100. In addition, the barrier height for hole movement is approximately 5.0 eV, which is prohibitively high for any hole movement under conventional operating voltages. As a result, hole movement in the prior art is not a factor in any programming or erasing scheme.
Conventional processes result in structures with such prohibitively high barrier heights, as well as less than ideal dielectric constants. For instance, oxynitrides for tunnel oxide dielectrics are produced conventionally by nitridation annealing of silicon oxide. However, oxynitrides produced by such conventional processes contain very little nitrogen. Further, the distribution of that nitrogen is far from uniform throughout the film. This relative paucity of nitrogen within oxynitride tunnel oxide dielectrics, as well as the relative heterogeneity of nitrogen distribution therein neither significantly increases the dielectric constant of the tunnel oxide dielectric, nor significantly decrease the barrier height. Conventional processes therefore are found wanting for ameliorating the problems of capacitance and barrier height.